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An equivalent thermal conductivity model of TSV arrays for thermal analysis in 3-D integrated circuits

As the CMOS technology continuously scales down into the deep submicron regime and approaches the physical limits of minimization, Moore's Law is hindered. The proposed three-dimensional integrated circuit (3-D IC) technology based on through silicon via (TSVs) brings hope. Although 3-D ICs bring many advantages over 2-D ICs, the thermal management challenges still need to be addressed effectively. TSVs carry signals while facilitating the thermal transfer of stacked chips due to their high thermal conductivity and offer a potential thermal management solution for 3-D ICs. The TSVs are structured in arrays to significantly improve heat dissipation. This paper proposes a cellular array structure that offers better heat dissipation capabilities compared to conventional rectangular arrays. First, the TSV cellular arrangement is described. Secondly, a method for modelling the equivalent thermal conductivity (ETC) of TSV arrays is proposed. Finally, the excellent performance of the cellular structure on thermal conductivity is verified by a comparative analysis of the thermal characteristics of the TSV array in the COMSOL system using finite element method(FEM). The results presented in this paper are beneficial for designers to optimise the TSV array arrangement and predict the thermal performance of TSV arrays. In addition, it provides a reference for 3-D IC reliability design.
PAPER REVISED: 2024-04-01
PAPER ACCEPTED: 2024-04-19
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